Analyse et modélisation des phénomènes de mismatch des transistors MOSFET avancées

For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed.Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés

Novel concept of gas sensitivity characterization of materials suited for implementation in FET-based gas sensors

Abstract : We propose a novel technique to investigate the gas sensitivity of materials for implementation in field-effect transistor-based gas sensors. Our technique is based on the measurement of the surface charge induced by gas species adsorption, using an electrometer. Platinum sensitivity to hydrogen diluted in synthetic air has been evaluated with the proposed charge measurement technique in the operation temperature range from 80 to 190 °C at constant H2 concentration of 4 % and for different concentrations ranging from 0.5 to 4 % at 130 °C

Analysis and modeling of mismatch phenomena for advanced MOSFET‟s

Afin de réaliser correctement leur fonction, certains blocs analogiques ou numériques comme les miroirs de courant ou les SRAM, nécessitent des paires de transistors MOS électriquement identiques. Cependant, les dispositifs sur silicium, même appariés, subissent des variations locales aléatoires ce qui fait varier leurs performances électriques. Ce phénomène est connu sous le nom désappariement. L'objectif de cette thèse est de comprendre les causes physiques de ce désappariement, de le quantifier et de proposer des solutions pour le réduire. Dans ce contexte, quatre thèmes principaux sont développés. Le premier thème se focalise sur l'optimisation des méthodologies de mesures des phénomènes de désappariement. Une nouvelle méthode de mesure du désappariement de Vt et de β ainsi qu'un nouveau modèle de désappariement de ID sont proposés, analysés et appliqués à des données mesurées sur des technologies 28nm Bulk et FD SOI. Le second thème se concentre sur la caractérisation des différentes configurations de transistor MOS afin de proposer l'architecture optimale en fonction des applications visées. Ainsi, la possibilité de remplacer le LDEMOS par une configuration cascode est analysée en détail. Le troisième thème se focalise sur l'analyse et la modélisation des phénomènes de désappariement des transistors MOS avancés. Trois aspects sont analysés : 1) l'introduction du Ge dans le canal P des technologies 28nm BULK, 2) la suppression de la contribution de la grille sur le désappariement de Vt en utilisant la technologie 20 nm métal-Gate-Last 3) un descriptif des principaux contributeurs au désappariement de Vt, β et ID dans les technologies 28 et 14nm FD SOI. Le dernier thème traite du comportement du désappariement des transistors MOS après vieillissement. Un vieillissement NBTI a été appliqué sur des PMOS de la technologie 28nm FD SOI. Des modèles de comportement de Vt et de β en fonction du nombre de charges fixes ou d'états d'interfaces induits à l'interface Si/SiO2 ou dans l'oxyde sont proposés et analysés.For correct operation, certain analog and digital circuits, such as current mirrors or SRAM, require pairs of MOS transistors that are electrically identical. Real devices, however, suffer from random local variations in the electrical parameters, a problem referred to as mismatch. The aim of this thesis is to understand the physical causes of mismatch, to quantify this phenomenon, and to propose solutions that enable to reduce its effects. In this context, four major areas are treated. The first one focuses on the optimization of mismatch measurement methodologies. A new technique for the measurement of Vt and β mismatch and an ID mismatch model are proposed, analyzed and applied to experimental data for 28 nm Bulk and FD SOI technologies. The second area focuses on the characterization of different configurations of MOS transistors in order to propose design architectures that are optimized for certain applications. Specifically, the possibility of replacing LDEMOS with transistors in cascode configuration is analyzed. The third area focuses on the analysis and modeling of mismatch phenomena in advanced Bulk and SOI transistors. Three aspects are analyzed: 1) the impact of the introduction of germanium in P channel of 28nm BULK transistors; 2) the elimination of the metal gate contribution to Vt mismatch by using 20nm Gate-last Bulk technology; 3) a descriptive study of the principal contributions to Vt, β and ID mismatch in 28 and 14 nm FD SOI technologies. The last area treats the mismatch trends with transistor aging. NBTI stress tests were applied to PMOS 28nm FD SOI transistors. Models of the Vt and β mismatch trends as a function of the induced interface traps and fixed charges at the Si/SiO2 interface and in the oxide were developed and discussed

Cascode configuration as a substitute to LDE MOSFET for improved electrical mismatch performance

session 10: matchingInternational audienceThe work presented in this paper investigates the possibility of replacing a Lateral Drain Extended MOS (LDEMOS) SOI transistors by a cascode configuration to improve the electrical mismatch performance. The cascode connection of two MOS devices is known to sustain as high drain voltage as LDEMOS SOI transistors and offers the same mismatch robustness of Silicon On Insulator (SOI) MOS transistors. The individual mismatch constants associated to Vt (iA Δvt ), β (iA Δβ/β ) and Id (iA ΔId/Id ) for the presented cascode configuration are shown to have similar values to those reported for individual MOS devices

Mismatch trends in 20nm gate-last bulk CMOS technology

session posterInternational audienceIn this work Vt and β mismatch for the 20 nm Gate-last bulk CMOS technology are investigated for the first time. Our results indicate that the 20 nm Gate-last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-first counterpart. Furthermore, the evolution of the Vt and β mismatch parameters, iA ΔVt and iA Δβ/β , is analyzed as a function of EOT (Tox) from the 90 nm technology node down to the 20 nm technology node. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot iA ΔVt vs EOT is observed from the 28 nm Gate-first technology, with such offset approaching zero for the 20 nm Gate-last technology node. This indicates evidence of a huge decrease in the mismatch contribution of the gate material

A comparative mismatch study of the 20nm Gate-Last and 28nm Gate-First bulk CMOS technologies

International audienceIn this work the threshold voltage (Vt), the current gain factor (β), and the drain current (ID) mismatch trends for 20 nm Gate-Last bulk CMOS technology integrating High-k/metal gate are investigated. The reported results indicate that the high k/metal Gate-Last technology exhibits a reduced metal gate granularity contribution to the Vt mismatch and good performance in terms of the β mismatch. This study further demonstrates that the ID variability mainly depends on the mismatch trends of Vt and β, and on the contributions of the transconductance divided by the drain current (Gm/ID) and the source drain series resistance (Rsd) terms. The 20 nm Gate-Last technology exhibits significant improvement in the Vt and β mismatch performance as compared to the 28 nm Gate-First counterpart. The evolution of the Vt and β mismatch parameters, iAΔVt and iAΔβ/β, is further analyzed as a function of the electrical oxide thickness EOT (Tox) along the technology nodes from 90 nm to 20 nm. A clear trend towards a reduction of the y-axis intercept (i.e. offset) of the linear plot of iAΔVt as a function of EOT is observed starting at the 28 nm Gate-First technology, with the offset approaching zero for the 20 nm Gate-Last technology node. This observation point out a considerable decrease of the gate material contribution to mismatch performances

Crustal configuration in the northern Levant basin based on seismic interpretation and numerical modeling

International audienceThe interpretation of five 2D PSTM seismic reflection sections (14 s TWT) covering the northern Levant Basin revealed a total of 10 horizons, among which, one is interpreted as an interface that may represent the Moho. The interpretation of seismic packages and their bounding surfaces as well as the seismic facies analysis were constrained by published 2D seismic interpretations of the northern Lebanese offshore. A total of nine seismic packages are identified in the basin with ages varying from the Mid Jurassic to the Quaternary. The filling of the basin is made up of thick Cenozoic and Mesozoic strata deposited above rifted Triassic – Early Jurassic interval. The sediments are deposited in deep water mixed-settings resulting from high-stand systems (various types of carbonate platforms) and low-stand systems (siliciclastic and carbonate deep-water turbidite complexes). Carbonate and siliciclastic systems are sealed by 1–1.5 km of evaporites, and underlie Plio-Quaternary hemipelagic and pelagic sediments intercalated by turbiditic sheets.The time horizons were converted into depth using two methods; the first one is based on stacking velocities and the second one on velocities resulting from refraction data. 2D crustal modeling was achieved by integrating free-air gravity anomaly, geoid heights and topography data on the five interpreted PSTM seismic lines. The models representing five sections across the northern Levant Basin, show a progressively attenuated crystalline crust in an EW direction (away from the basin's eastern margin). The crystalline crust is best interpreted as a strongly thinned continental crust under the Levant Basin, represented by two distinct components, an upper and a lower continental crust. The Moho appears to be situated between 20 and 23 km in the central and southern Lebanese offshore. Estimated surface heatflow in the basin is around 40 mW/m2, which is lower than reported values for the onshore and the margin. These differences in heatflow values between the offshore, the margin and the onshore have an important impact on hydrocarbon maturation and assessment of potential petroleum systems

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

International audienc

High sensitivity pH sensing on the BEOL of industrial FDSOI transistors

International audienc

Thiopurine metabolite measurement leads to changes in management of inflammatory bowel disease

Background: The thiopurines azathioprine and 6-mercaptopurine are recommended for maintenance of remission in inflammatory bowel disease (IBD). Measurement of concentrations of the metabolites 6-thioguanine nucleotide and 6-methylmercaptopurine helps delineate interindividual variation in metabolism that may underlie variability in efficacy and toxicity. Aims: We aimed to perform a retrospective observational study to determine the utility of thiopurine metabolite testing following its introduction into South Australia. Methods: All patients having thiopurine metabolite tests done at Flinders Medical Centre between November 2008 and January 2010 were identified. Case notes of patients with testing done in the context of treatment for IBD were interrogated to determine the reason for testing, clinical context and outcome. Results: One hundred and fifty-one patients were identified with thiopurine metabolite testing for IBD with 157 testing episodes. Eighty (51.0%) had testing done for flare or inefficacy, 18 (11.5%) for adverse effects, 5 (3.2%) for a combination of inefficacy and adverse effects, and 54 (34.4%) for routine or other reasons. Testing was followed by improved outcomes of increased efficacy, reduced toxicity or change to alternative therapy in 55.0% of the inefficacy/flare group, 27.8% of the suspected adverse reaction group, 60.0% of the combination group, and 13.0% of the routine/other group. Allopurinol was used as cotherapy in 16 patients and led to marked improvements in metabolite concentrations. Conclusions: Thiopurine metabolite testing has quickly become established in South Australia. When used for inefficacy or adverse effects, it often leads to improved outcomes. Prospective studies are needed to determine whether routine testing to guide dosing is of benefit.N. A. Kennedy, T. L. Asser, R. E. Mountifield, M. P. Doogue, J. M. Andrews and P. A. Bampto